Up for Scraps — Sources

External companion to the long-read. Citation chain for every load-bearing claim, organised by section. Where claims involve estimation or inference, the methodology is named explicitly.

§1 — The $599 question

MacBook Neo product facts

Claims in prose: Apple announced a $599 laptop on 4 March 2026. The MacBook Neo runs an A18 Pro die with one defective GPU core fused off (5 GPU cores vs 6 on the iPhone 16 Pro variant). Cook on the Q1 earnings call: “best launch week ever for first-time Mac customers.” Apple in supply chase mode by April; sold out for April per 9to5Mac.

Specifications:

  • Announced 4 March 2026; released 11 March 2026
  • Pricing: $599 standard / $499 education
  • A18 Pro chip — same SoC as iPhone 16 Pro, with 5-core GPU (one core fused off) vs iPhone 16 Pro’s 6-core
  • 8GB unified memory, 256GB SSD baseline
  • Performance benchmarks: outperforms M1 MacBook Air (Geekbench 6: 3,461 single-core, 8,668 multi-core, 31,286 Metal); outperforms iPad Air M3 in single-core
  • Apple-claimed comparisons: up to 50% faster than bestselling Intel Core Ultra 5 PC laptop on everyday tasks; up to 3× faster on on-device AI workloads

Sales / supply:

  • Initial Apple production plan: 5-6 million units in 2026
  • Revised after first-week demand: 10 million units (per Tim Culpan / Culpium, summarised in MacRumors)
  • Foxconn and Quanta as primary contract manufacturers, both in supply chase mode
  • Apple online store delivery estimates: 2-3 weeks (US), 1-2 weeks (Japan) as of mid-April 2026
  • “Sold out for April” status confirmed mid-April 2026 (9to5Mac)

Sources:

Hsu and Wu reactions

Claims in prose:

  • Hsu (Asus co-CEO): described the Neo on the Q4 2025 earnings call as a “content consumption” device, similar in his framing to an iPad rather than to a mainstream notebook
  • Wu (Asus CFO Nick Wu): “shock to the entire market”

Attribution discipline: “Content consumption” is Hsu’s verbatim phrase. “Similar to an iPad” is the journalist’s gloss in 9to5Mac coverage of his Q4 2025 earnings call statement, not a direct Hsu quote. The piece preserves the distinction by quoting only the verbatim phrase and paraphrasing the comparative.

Sources:

Four-tier binning hierarchy

Claims in prose: Apple operates a four-tier binning hierarchy across each chip generation. Two die designs (A-series and A-series Pro) each producing two commercial bins.

GenerationBinGPU coresProductPriceStatus
A18 (TSMC N3E)A18 Pro full-spec6-coreiPhone 16 Pro / Pro Max$999+Released Sep 2024
A18 (TSMC N3E)A18 Pro binned5-coreMacBook Neo$599 / $499 eduReleased Mar 2026
A18 (TSMC N3E)A18 full-spec5-coreiPhone 16 / 16 Plus$799Released Sep 2024
A18 (TSMC N3E)A18 binned4-coreiPhone 16e$599Released Feb 2025
A19 (TSMC N3P)A19 Pro full-spec6-coreiPhone 17 Pro / Pro Max$999+Released Sep 2025
A19 (TSMC N3P)A19 Pro binned5-coreNext-gen MacBook Neo$599 (rumoured)Rumoured 2026 (Culpan)
A19 (TSMC N3P)A19 full-spec5-coreiPhone 17 / Plus$799Released Sep 2025
A19 (TSMC N3P)A19 binned4-coreiPhone 17e$599Released Mar 2026

Note on production line status (mid-2026): A18 / A18 Pro production wound down for primary iPhone use (iPhone 17 family launched Sep 2025 on N3P) but continues for: continued sale of iPhone 16 / 16 Plus / 16e (still in Apple’s lineup), MacBook Neo (only product still launching with A18 Pro), inventory and aftermarket needs. The Neo’s silicon supply is therefore drawing from a legacy production line, which gives Apple a one-generation lag on the laptop line that further compresses cost basis.

Sources:

Budget laptop market context

Claims in prose: A segment that ships 40-60 million units a year, dominated by HP, Lenovo and Dell with razor-thin margins. IDC slashed its 2026 PC shipment forecast three times in four months, from -2.4% in November 2025 to -11.3% in March 2026. Dell raised prices 15-20% in mid-December. ASUS warned customers of 25-30% price rises in Q2.

Supporting data:

  • 2024 total PC shipments (IDC): 262.7M units, up 1% YoY
  • 2024 notebook/laptop shipments specifically: ~187M units (laptops are roughly 70% of total PC market)
  • Mobile (laptop) CPU market share Q4 2025 (Mercury Research): Intel 74%, AMD 26%
  • Sub-$500 budget laptops: ~42% of Asia-Pacific laptop sales, implying global budget segment in 40-60M unit range annually
  • Education segment alone deployed >50M units in 2022

Sources:

§2 — The flywheel

A18 Pro / A18 die specifications

  • A18 Pro die size: 105 mm² (TSMC N3E)
  • A18 die size: 90 mm² (TSMC N3E)
  • A17 Pro (predecessor): 103.8 mm² (for context)
  • TSMC N3E is second-generation 3nm, with better yield and lower cost than original N3B

Sources: TweakTown (TechInsights derived), Wikipedia A18 entry, MacRumors

iPhone production volumes

  • 2024 total iPhone shipments: 225.7M (IDC / Backlinko)
  • 2023 total: 231.8M
  • iPhone 16 series production target: ~90M units in H2 2024 alone (Bloomberg / Apple supply chain)
  • iPhone 16 Pro / Pro Max: ~67% of iPhone 16 mix → ~60M Pro units with A18 Pro
  • iPhone 16 / Plus: ~33% → ~30M units with A18

TSMC N3 capacity

  • Late 2025 monthly N3 capacity: surpassed 150,000 wafers/month
  • End 2026 target: ~140-160k wafers/month (analysts revised down from earlier 180-200k targets due to capacity constraints)
  • Capacity coming primarily from Fab 18 in Tainan
  • 3nm contributed 24% of TSMC 2024 revenue (Wccftech via Commercial Times)
  • Apple is the dominant N3 customer; Nvidia, Qualcomm, MediaTek, AMD also using N3E

Sources: Global Semi Research, Wccftech, R&D World — varied analyst estimates; TSMC publishes only aggregate fab data.

Wafer math

The piece’s claim that the iPhone 16 production line consumes ~180,000 N3E wafers per year, and that this represents 15-20% of TSMC’s leading-edge capacity, is a back-calculation. Methodology:

A18 Pro: 60M units × 105mm² die / ~600 dies per 300mm wafer / yield = ~125,000 wafers/year at mature yield rates A18: 30M units × 90mm² / ~700 dies per wafer / yield = ~54,000 wafers/year at mature yield rates Total iPhone 16 N3E consumption: ~180,000 wafers/year

Against 2024 N3 capacity ramp from ~70k to ~125k wafers/month (avg ~95k = ~1.14M wafers/year), Apple iPhone alone ≈ 15-20% of total N3 family output. Adding M-series volumes (estimated 30-40M Mac/iPad units annually, larger dies), Apple total exceeds 25-30% of N3 capacity.

N3E yield trajectory — load-bearing for the binning argument

TSMC does not publish node-specific yield data. The figures in the piece are analyst estimates derived from die-per-wafer economics and supply-chain reporting. The piece flags this explicitly in §2 prose: “TSMC does not publish node-specific yield data; the figures that follow are analyst estimates derived from die-per-wafer economics and supply-chain reporting.”

Yield trajectory:

  • N3B (first-gen 3nm, used for A17 Pro and M3): yield started at ~55% at HVM ramp (mid-2023)
  • N3E (used for A18, A18 Pro, A19 series): yield started ~60% at Q4 2023 HVM ramp, climbed roughly 5 percentage points per quarter, reached low 80s by late 2024
  • 2024 average yield: ~72% — the figure used in the piece’s wafer-math back-calculation
  • Apple’s “wafer buy” deal: Apple pays only for functional chips (“pay per good die”) — TSMC absorbs the yield risk during ramp
  • Apple was 100% of N3 (N3B) production capacity during the first generation; this contractual structure continued into N3E for iPhone 16

Binned tail derivation (analyst estimate):

  • Of every 100 A18 Pro dies that come off the wafer at 2024 average yield: ~72 pass with all six GPU cores functional, ~14-18 are functional with one defective GPU core (binned A18 Pro suitable for MacBook Neo), ~10-14 are unrecoverable
  • At 60M iPhone 16 Pro production volumes, the binned tail runs to ~12-15 million dies a year
  • Against the 40-60M unit budget laptop CPU market, this represents roughly a fifth to a third of the segment

Sources:

Historical analogy: x86 server market 1990s

The claim that Intel’s Pentium server chips shared microarchitecture and process node with the desktop Pentium that was selling tens of millions of units a year is reference-level material. Specific Intel reference: Pentium Pro / Xeon shared microarchitecture with desktop Pentium II. This is well-documented in standard semiconductor industrial economics literature; no controversy.

x86 µop architecture (closing block of §2)

General computer architecture knowledge — verifiable from Intel/AMD optimisation manuals:

  • Intel Core µop cache: ~1,500 µops, decoded x86 instructions cached post-decode
  • AMD Zen µop cache equivalent: ~4,000 ops
  • x86 decode complexity: variable-length instructions (1-15 bytes), multiple decoders required, complex prefix handling
  • Decode frontend die area: contested estimate 5-15% of core area, depending on configuration and definition

Sources: Intel Software Optimisation Reference Manual; AMD Software Optimization Guide for AMD Family 19h Processors.

§3 — Who can run the flywheel

Apple Silicon

  • M1 launched November 2020; full Mac transition complete by mid-2023
  • Current generation: M4 family (2024); M5 expected late 2026
  • Custom ARM cores: Firestorm/Icestorm → Avalanche/Blizzard → Everest/Sawtooth (M4)
  • A-series and M-series share core architecture; M-series adds GPU cores, larger memory channels, higher TDP envelope

Apple M-series TSO hardware mode (Rosetta 2 enabling mechanism)

Claims in prose: Apple’s M-series cores have a hardware mode for the strict memory consistency model x86 enforces, switchable at runtime. When Rosetta 2 is translating an x86 binary, the CPU itself enforces x86 memory semantics. The performance cost of this mode is around nine per cent on average. Rosetta 2 runs at 70-80% of native x86 performance.

Technical details:

  • Apple M1/M2/M3/M4 cores implement two memory consistency models in hardware: ARMv8.3-A weak memory ordering (default) and Total Store Ordering (TSO, x86’s strict model)
  • TSO mode is enabled by setting bit 0 of the ACTLR_EL1 control register
  • When Rosetta 2 is translating x86_64 binaries, the OS switches the executing core to TSO mode for that process
  • Native ARM code continues to run in weak memory ordering mode
  • Performance cost of TSO mode: ~9% on average (8.94% per academic benchmarking on SPEC CPU 2017)
  • The alternative — software emulation of x86 memory ordering via inserted fence instructions — is much more expensive (compiler must conservatively insert fences anywhere a memory ordering dependency might exist; placement of fences for correctness is undecidable in general)

Sources:

Apple A18 Pro phone-derived I/O constraints in the Neo

Claims in prose: The A18 Pro was designed for a phone, and the Neo carries the phone’s I/O constraints with it: two USB-C ports rather than four, only one of them USB-3, no Thunderbolt, Wi-Fi 6E rather than Wi-Fi 7.

Source confirmation: John Gruber (Daring Fireball) via Macworld — “the original chip and logic board were only designed for a single USB-C port with USB-3 speeds. That means that at some point during the Neo’s development, Apple decided the Neo needed two USB-C ports and had to perform some engineering magic to bring an extra port.”

The piece’s structural claim — that no other vendor in the budget laptop segment could ship those concessions at $599 and survive — is analytical, not sourced. The factual concessions themselves are documented from MacBook Neo specifications and tech press analysis.

Qualcomm Snapdragon X — failure case

Claims in prose: Q3 2024 market share 0.8%, 720,000 units against a global notebook market of 66 million in that quarter. Qualcomm’s stated ambition for the segment was meaningfully higher. By late 2025 visibly hedging with Snapdragon X chips appearing in Android 16 compatibility tables and a pivot toward Android laptops emerging as the public strategy.

Supporting data:

  • Snapdragon X Elite launch: mid-2024
  • Snapdragon X2 Elite Extreme launched Snapdragon Summit 2025 (September 2025): 18 cores (12 Prime + 6 Performance), 4.4 GHz max clock, 80% GPU performance gain over X Elite, 120W TDP
  • Compatibility ecosystem (per Qualcomm): 750+ native apps, 1,400+ games, 93% native performance
  • App compatibility remains the structural problem; gaming particularly weak due to anti-cheat software
  • Microsoft Prism translation layer for Windows on ARM has had a slower trajectory than Rosetta 2; structural reason given in prose: Microsoft has no incentive to break the x86 OEM ecosystem that ships most copies of Windows

On “stated ambition” framing: The piece deliberately uses softer framing (“stated ambition…meaningfully higher than the result”) rather than a specific market-share target figure. Qualcomm management has made various public statements about Snapdragon X aspirations; the softer framing is defensible from the broader pattern without overcommitting to a specific projection.

Sources:

MediaTek

Claims in prose: Taiwanese low-profile powerhouse that ships half a billion smartphone and embedded SoCs a year. Co-designed the GB10 chip in Nvidia’s $3,999 DGX Spark personal AI workstation: a 20-core ARM CPU paired with a Blackwell GPU on a coherent fabric.

Supporting data:

  • Wi-Fi chipset market 2024: Broadcom 20-25%, Qualcomm 18-23%, MediaTek 15-20%, Intel 5-10%, Realtek 4-8%
  • Wi-Fi 7 specifically: MediaTek self-described as leading provider of Wi-Fi 7 home gateway and extender chipsets
  • Filogic chipset deployment in Tier 1 service provider gateways across the US, Europe, and Asia
  • GB10 / DGX Spark co-design with Nvidia confirmed (see §4 Nvidia entry)

Sources:

Chinese SoC tier — Rockchip and Allwinner

Claims in prose: Rockchip’s flagship parts use ARM Cortex-A application cores; every successive generation has added more RISC-V silicon as auxiliary or accelerator content. The recent RV1106 already shipped with an ARM Cortex-A7 main core paired with a RISC-V MCU on-die. The RK182X coprocessor announced in July 2025 is a multi-core RISC-V chip dedicated to running 3-billion- and 7-billion-parameter large language models locally. Allwinner’s D1 series, in production since 2021, was the world’s first general-purpose SoC built on T-Head’s open-source XuanTie RISC-V core.

Rockchip RK182X specification (announced Rockchip Developer Conference 2025, Fuzhou, July 2025):

  • RK1820: 3B-parameter LLM/VLM coprocessor with 2.5GB RAM
  • RK1828: 7B-parameter LLM/VLM coprocessor with 5GB RAM
  • Multi-core RISC-V CPU; 3D-stacked DRAM
  • INT4/FP4 quantisation; 7B parameter models fit in 3.5GB RAM
  • PCIe 2.0, USB 3.0, Ethernet for connection to host application processor
  • Designed as attached accelerator for Rockchip RK3576/RK3588
  • Performance: ~2,000 tokens/s prefill, ~120 tokens/s decode (8-10× faster than running the same model on the RK3588’s NPU)
  • Software: RKNN3 toolkit, supports PyTorch, ONNX, TensorFlow, HuggingFace GGUF
  • Development kits shipping (Firefly RK182X 3D RAM Stacking Development Kit, $889/$1,029)
  • Next-generation RK1860 expected Q2/Q3 2026

RV1106 ARM Cortex-A7 + RISC-V MCU on-die: Rockchip RV1106 ships with an ARM Cortex-A7 main core paired with a Syntacore SCR1 RISC-V MCU. The same Syntacore RISC-V MCU exists in RK3568, RV1126, RV1106. Pattern of RISC-V auxiliary content in ARM-flagship Rockchip silicon precedes the RK182X by several generations.

Allwinner D1:

  • Released 2021
  • Described as “the world’s first general-purpose SoC developed based on the XuanTie C906” (RISC-V, 64-bit)
  • Allwinner V85X series and R128 series also RISC-V
  • Allwinner is partner in T-Head’s “XuanTie preferred chip program”
  • Allwinner ships A-series (ARM) for tablets, D-series (RISC-V) for industrial/IoT, R128 (RISC-V) for intelligent voice — explicit dual-track strategy

Sources:

§4 — The cloud and AI version

AWS Graviton

Claims in prose:

  • Graviton 1 shipped in 2018 (design work underway by 2016; strategic decision earlier)
  • Graviton 4: 96 Neoverse-V2 cores, GA July 2024
  • Brown re:Invent 2024 disclosure: “more than half of new EC2 vCPU capacity added across the prior two years” had been Graviton rather than x86
  • Q4 2025 Amazon earnings: most new compute capacity was Graviton; 90% of AWS top 1,000 customers had Graviton in production; chips business (Graviton + Trainium) exceeding $10bn annualised run rate, growing at triple-digit rates YoY

Supporting data:

  • Generation timeline: G1 (2018), G2 (2019), G3 (2021), G4 (announced 2023, GA July 2024)
  • 2 million Graviton CPUs deployed as of mid-2024 across 30 regions, 150+ instance types (per Rahul Kulkarni, AWS)
  • Performance/cost: 30% better performance gen-on-gen; 40% better price-performance vs x86; up to 60% lower energy consumption
  • AWS top 100 customers all running production Graviton workloads; 50,000+ customers using Graviton meaningfully

Attribution discipline: The “more than half of new EC2 vCPU capacity added across the prior two years” figure is Brown’s verbatim phrasing at re:Invent 2024 — refers to new capacity added, not installed base. The “most new compute capacity” figure is from the Q4 2025 Amazon earnings call. The two figures are distinct (different time windows and metrics) and the piece preserves the distinction.

Sources:

Nvidia Grace / Vera / Olympus

Claims in prose: Nvidia’s Grace CPU (announced 2022, shipping in volume in the Grace Hopper Superchip) is an ARM-based design with a 900GB/s coherent link to a Hopper or Blackwell GPU on the same package. The next-generation Vera CPU goes further: Nvidia is now designing custom ARM-compatible cores under its own microarchitecture programme (Olympus) rather than licensing Neoverse off the shelf.

Specifications:

  • Grace Superchip: 144 Arm Neoverse V2 cores, 1TB LPDDR5X with ECC, 1TB/s memory bandwidth, NVLink-C2C 900GB/s — Armv9-based
  • Grace Hopper Superchip: Grace CPU + Hopper GPU on coherent NVLink-C2C
  • Vera (next gen): custom Olympus ARM-compatible cores — Nvidia designing its own ARM-compatible microarchitecture, the same move Apple made with the A-series
  • Used in Los Alamos Venado supercomputer and other HPC deployments

On the architectural framing: The piece argues that the Grace CPU was designed to eliminate a structural bottleneck in conventional server architecture — the PCIe bus connecting CPU and GPU, which is designed for general expansion-card I/O rather than the streaming-throughput coherent-memory traffic AI training and inference workloads require. The 900GB/s NVLink-C2C figure is the technical anchor: against PCIe Gen5 x16’s ~63GB/s, NVLink-C2C is roughly an order of magnitude faster, treating CPU and GPU as a single coherent compute system rather than two devices on a shared bus.

Sources:

Nvidia CUDA-on-RISC-V port

Claims in prose: In July 2025, at the RISC-V Summit China in Shanghai, Nvidia’s vice-president of hardware engineering Frans Sijstermans announced that Nvidia is porting CUDA to RISC-V. The port targets the RVA23 RISC-V profile ratified in 2024. Nvidia framed the announcement as a “strategic technology disclosure” rather than a product launch, and has not committed to a release timeline. In a subsequent interview with RISC-V International, Sijstermans framed the rationale as structural: “as export controls and market fragmentation reshape the compute landscape, it’s increasingly important for foundational technologies like CUDA to be able to operate independently of any one architecture or licensing regime.”

Attribution discipline: The keynote announcement at RISC-V Summit China and the structural-rationale quote are from two separate venues. The keynote announced the port; the structural quote is from a follow-up interview with RISC-V International. The piece preserves this distinction.

Architectural meaning: RISC-V CPU as the host application processor in CUDA-based AI systems — running the OS, application logic, and CUDA system drivers — while Nvidia GPUs (Blackwell, future generations) handle parallel compute. Parallel to the existing Grace ARM CPU pattern.

Limits of the port:

  • The port targets RISC-V as host CPU only
  • Nvidia is not porting CUDA to target RISC-V devices (CUDA still compiles to Nvidia GPUs)
  • Nvidia GPUs already contain dozens of small RISC-V cores internally for control functions (NVDLA, GPU System Processor) — unrelated to this announcement
  • Development currently using SiFive HiFive Premier P550 board; expected to migrate to RVA23-compliant hardware once available
  • AMD’s ROCm already runs on RISC-V hosts; Nvidia’s announcement is in part a competitive response

Sources:

DGX Spark / GB10

Claims in prose: The DGX Spark, launched late 2025 at $3,999, closes the loop visually: a 20-core ARM CPU (the GB10, co-designed with MediaTek), a Blackwell GPU, 128 gigabytes of unified memory, all in a 170-watt desktop enclosure that delivers personal-AI-workstation performance.

Specifications:

  • 20 ARM cores (10× Cortex-X925 + 10× Cortex-A725)
  • 128GB LPDDR5X unified memory at 273GB/s
  • Blackwell GPU on package via NVLink-C2C
  • 200GbE ConnectX-7 networking
  • 170W total package
  • $3,999 retail
  • Co-designed with MediaTek

Sources: Serve The Home (March 2025), Signal65 (October 2025), Nvidia product announcements.

§5 — The incumbent trap

Intel x86-S — the canonical case

Claims in prose: Intel published the draft specification for x86-S in May 2023, a simplification proposal that would have removed virtually all legacy design elements. June 2024: Intel published revision 1.2. December 2024: Intel terminated the x86-S programme. Official statement cited “inputs from the ecosystem” and reaffirmed Intel’s “longstanding commitment to software compatibility.” A new x86 Ecosystem Advisory Group was formed with AMD and the major Windows OEMs as members. September 2025: AMD publicly stated that the ARM ISA does not offer an efficiency advantage over x86.

Specifications of x86-S proposal:

  • Would have removed: 16-bit modes, 32-bit protected modes, rings 1 and 2, legacy interrupt controllers
  • Would have enabled boot directly into 64-bit mode
  • Spec versions: initial May 2023, v1.2 June 2024
  • Intel statement on termination: “Based on inputs from the ecosystem, Intel has chosen not to pursue X86S. Intel will continue to maintain its longstanding commitment to software compatibility.”
  • Pivot: x86 Ecosystem Advisory Group with AMD, Microsoft, Lenovo, HP, Meta, and others (announced October 2024)

AMD pushback (September 2025): “AMD Claims Arm ISA Doesn’t Offer Efficiency Advantage Over x86” (TechPowerUp).

Sources:

Intel 18A / Panther Lake — supports the §5 hedge

Claim in prose: “Intel still sources key parts of its own new chips from TSMC.”

Panther Lake (Core Ultra Series 3) tile-level breakdown:

  • Intel’s flagship 2025/2026 client SoC, launched January 2026 at CES
  • Architectural design uses Intel’s tile/chiplet packaging (Foveros)
  • Compute tile (CPU cores): fabbed on Intel 18A
  • Graphics tile (Xe3 GPU): fabbed on TSMC N3
  • Platform Controller / I/O tiles: TSMC N6
  • Filler tiles: TSMC N6

The product strategy is explicit: Intel uses 18A where it offers advantage (compute density at advanced node), and TSMC where TSMC offers advantage (GPU process maturity, mature lower-cost nodes for I/O).

Significance for the hedge paragraph: Intel’s own flagship product still depends on TSMC for graphics and I/O silicon. If Intel 18A were competitively complete, Intel would be using it for all tiles; that they don’t is a real-time market signal of where Intel’s process actually stands relative to TSMC. This does not invalidate the hedge — Intel may yet succeed as a foundry, and Panther Lake represents a measured transition rather than a failure — but it anchors the “too early to call” framing in concrete present-tense evidence.

Sources:

  • Intel Newsroom, “Panther Lake Brings Intel 18A to Life” (January 2026 CES launch coverage)
  • Tom’s Hardware: Panther Lake architectural breakdown, January 2026
  • AnandTech / SemiAnalysis tile-level analysis of Panther Lake packaging
  • Industry confirmation that the GPU tile uses TSMC N3 (not Intel 18A)

§6 — Sovereign compute

US export control regime

Reference framework:

  • BIS October 2022 controls on advanced computing and semiconductor manufacturing
  • October 2023 update tightening AI chip controls (the “October Surprise” rules)
  • FDPR (Foreign Direct Product Rule) extensions
  • Entity List additions
  • Per-country license requirements for advanced semiconductor manufacturing equipment

Sources: US BIS announcements, primary.

ARM Ltd financials and royalty structure

Claims in prose: ARM Ltd, the British company spun out of Acorn in 1990, owned by Softbank since 2016, listed on Nasdaq since September 2023, owns the ARM ISA and licenses it to chip designers under royalty agreements. Royalty rates are not the dominant cost in chip economics — typically a low-single-digit percentage of selling price for architectural licensees, with Armv9 rates approximately double Armv8 rates — but they are a foreign-licensor dependency in the critical path of every sovereign compute design.

Supporting data:

  • FY2025 revenue: $4.007bn (FY2024: $3.233bn) — 24% YoY growth
  • Q2 FY26 royalty revenue: $620M (+21% YoY)
  • Three consecutive quarters >$1bn total revenue (royalty + licensing) by Q2 FY26
  • Armv9 royalty rates “typically at least double” Armv8 rates
  • Armv9 chips ~15% of royalty revenue (Q2 FY26), up from ~10% prior quarter and rising
  • Compute Subsystems (CSS) generating higher royalty rates per chip
  • China revenue: 27% of Arm revenues in 2021

Sources:

Arm China governance crisis — the textbook case

Claims in prose: Allen Wu, CEO of the Arm China JV, was fired by the board in June 2020 over conflicts of interest, refused to leave, and physically retained possession of the company’s official seal — under Chinese corporate law, the document that authorises board actions. Wu ran Arm China as a semi-independent operation for nearly two years, blocking outside audits and asserting Chinese sovereignty over the JV’s R&D output, until a Shenzhen court update of the business registration in April 2022 allowed his replacement.

Timeline:

  • 2018: Arm Ltd sold 51% of Arm China to Chinese investor consortium for $775M (Hopu Investment + others); Chinese partners gained majority control
  • June 2020: Board fires CEO Allen Wu over conflicts of interest (he had created a competing investment fund); Wu refuses to leave; retains physical possession of company seal/chops
  • 2020-2022: Two-year governance limbo. Wu operates Arm China independently, declares its own R&D team of 400+, blocks audits, refuses outside executive visits
  • 2022: SoftBank moves stake into SPV jointly owned with Arm Ltd, threatens to cut off new IP licensing if Wu remains
  • April 2022: Shenzhen government finally agrees to update business registration without Wu cited as legal representative; Liu Renchen (Tsinghua research institute, Shenzhen) and Eric Chen (SoftBank Vision Fund) appointed co-CEOs
  • Post-resolution: Wu nominally ousted, SoftBank/Arm regain governance control, but the JV remains the exclusive commercial distribution channel for Arm IP into China

The structural significance: Every Chinese chip designer using Arm IP must go through Arm China, which is structurally subject to PRC government influence. At the time of the Allen Wu crisis, China represented ~27% of Arm’s global revenue (2021). The piece’s claim that ARM dependency “can be contested, captured, or held up” is directly demonstrated by this case.

Sources:

RISC-V International governance

Claims in prose: The RISC-V instruction set is governed by RISC-V International, a Swiss-incorporated standards body. There is no licensor in the critical path, no royalty, and no governance capture available. The architecture is the equivalent of TCP/IP: a published specification anyone can implement.

Background:

  • RISC-V International incorporated in Switzerland (deliberately moved from US in 2020 to avoid jurisdiction concerns)
  • Open standards body governing the ISA
  • Major members include SiFive, Western Digital, Google, Nvidia, Intel, Tenstorrent, Alibaba/T-Head, others
  • Status as a Swiss standards body is the structural feature that distinguishes RISC-V from ARM Ltd dependency-wise

EU — European Processor Initiative and SiPearl

Claims in prose: SiPearl is a French-incorporated chip designer founded inside EPI, capitalised through a series of EuroHPC and France 2030 grants alongside a roughly hundred-and-thirty-million-euro Series A. The Rhea-1 processor taped out in November 2025 and will sample in early 2026 inside JUPITER, Europe’s first exascale supercomputer at Forschungszentrum Jülich. Rhea-2 is scheduled for 2026 in Europe’s second exascale system, the Jules Verne installation in France. The EPI roadmap explicitly includes RISC-V acceleration components, and the EU’s separate DARE programme is funding RISC-V development directly.

Timeline:

  • EPI launched 2018, three phases (2018-2021, 2022-2025, ongoing)
  • SiPearl founded out of EPI to commercialise Rhea processor
  • Series A funding: ~€130M closed in three tranches (2023-2025)
  • Rhea-1 tape-out: November 2025
  • Rhea-1 sampling: early 2026
  • Rhea-1 specifications: 80 (or 72, sources vary) Arm Neoverse V1 cores, 256-bit SVE units, HBM2E + DDR5 memory, PCIe with CXL, manufactured on TSMC N6
  • Rhea-1 deployment: JUPITER supercomputer at Forschungszentrum Jülich, going online in 2026
  • Rhea-2 scheduled for 2026/27, dual-chiplet design, more advanced process node, expected to use Arm Neoverse V3
  • Rhea-2 deployment: Alice Recoque / Jules Verne supercomputer, France-based, managed by GENCI

EPI roadmap on RISC-V: “EU-funded EPI has pushed aggressively to adopt the RISC-V architecture” (HPCwire). The transition path from ARM to RISC-V is implicit in the EPI roadmap progression. The DARE programme funds RISC-V development directly.

Sources:

China — T-Head, XuanTie, and EUV development

Claims in prose: T-Head, the Alibaba semiconductor subsidiary, has shipped over four billion XuanTie cores cumulatively, with the open-source variants on GitHub since 2021. The server-grade XuanTie C930 launched in February 2025; the C950, with eight-instruction decode and a sixteen-stage pipeline, entered production in early 2026 with reported initial deliveries of 470,000 units and a ten-billion-yuan annualised run rate. Alibaba Cloud’s senior executives have stated publicly that they expect RISC-V to become a mainstream cloud architecture within five to eight years. A domestic EUV prototype based on laser-induced discharge plasma — a different physical principle from ASML’s laser-produced plasma — has been operating at Huawei’s Dongguan facility since early 2025, with trial production targeted for 2025 and commercial-grade five-nanometre output projected for 2028.

XuanTie deployment:

  • Cumulative shipments: 4+ billion units (as of March 2024, per Damo Academy)
  • C930 server-grade RISC-V launched February 2025
  • C950 launched 2026, with 470,000 units delivered by Feb 2026 and annualised revenue surpassing ¥10bn (~$1.4bn)
  • C930/C950 specs: 8-instruction decode, 16-stage pipeline, out-of-order window >1,000 instructions, single-core SPECint2006 score >70, max 3.2 GHz
  • Open-sourced T-Head cores (E902, E906, C906, C910 → OpenE/C variants on GitHub) — published October 2021
  • C950 manufactured on TSMC 5nm process (per Nikkei sources) — note: even Chinese RISC-V leaders depend on TSMC for advanced nodes
  • Other Chinese RISC-V players: SpacemiT, Andes

Chinese EUV programme:

  • Working LDP-based EUV prototype at Huawei Dongguan facility, completed early 2025 — fundamentally different architecture from ASML (laser-induced discharge plasma vs laser-produced plasma)
  • Built by team including former ASML engineers, using parts from older ASML machines obtained on secondary markets
  • 2025 trial production target; 2026 mass production target; commercial 5nm by 2028 per multiple analyst sources
  • Power output: 100-150W achieved (mid-2025); 250W+ needed for high-volume manufacturing — gap is engineering, not physics
  • Conversion efficiency: 3.42% achieved by Lin Nan team (Beihang University), exceeding ARCNL’s 2019 figure of 3.2%; theoretical 6%, commercial threshold 5.5%
  • Parallel SSMB (Steady-State Micro-Bunching) approach at Tsinghua, using particle accelerator/synchrotron — theoretical >1kW output. Construction began Xiong’an, early 2025
  • DUV-SAQP bridge (interim): SMIC running 5nm pilot for Huawei Ascend AI chips at 30-35% yield via quadruple patterning
  • Coordination scale: 3,000+ researchers across Harbin Institute of Technology (light source), Changchun Institute of Optics (optical systems), SMEE (integration), Huawei, SiCarrier
  • Commercial parity timeline: 2028-2030 per most analyst estimates — significantly faster than the “many many years” ASML CEO timeline from April 2025

Sources:

India — India Semiconductor Mission and DIR-V

Claims in prose: The India Semiconductor Mission 1.0, approved December 2021 with a seventy-six-thousand-crore (roughly ten billion dollar) incentive framework, has approved ten projects across six states with total investment commitments of around nineteen billion dollars by end-2025. The Digital India RISC-V Programme, run under the Ministry of Electronics and Information Technology, funds an indigenous-processor portfolio of half a dozen named families, all RISC-V, all explicitly framed in Indian government communications as eliminating “license costs” and supporting “digital sovereignty.” India does not yet have a comparable operational deliverable to Europe’s JUPITER tape-out or China’s XuanTie production volumes, but the policy commitment is the most explicit on the record. The phrase “digital sovereignty” appears in the Indian government’s own press releases.

India Semiconductor Mission programme:

  • ISM 1.0 launched December 2021 with ₹76,000 crore (~$10bn) incentive framework
  • Up to 50% fiscal support for fabs, OSAT, chip design
  • As of December 2025: 10 projects approved across 6 states with ₹1.60 lakh crore (~$19bn) total investment
  • Tata Electronics fab (Dholera, Gujarat) — still in construction as of April 2026; first commercial production targeted December 2026; for mature nodes (28-90nm), not advanced nodes
  • CG Power packaging facility (Sanand) among other approved projects
  • ISM 2.0 announced Union Budget 2026-27: ₹1,000 crore initial allocation, focus shift to advanced manufacturing, equipment & materials, design IP

Indigenous RISC-V processor portfolio (DIR-V Programme):

  • SHAKTI (IIT Madras, RISC-V, since 2013) — academic core
  • AJIT (IIT Bombay, India’s first commercial microprocessor)
  • VIKRAM, THEJAS, DHANUSH, DHANUSH+ (System on Chips variants)
  • DHRUV64 announced October 2025 — 7nm indigenous processor design initiative
  • Government framing: RISC-V “eliminates license costs and enables collaborative innovation”
  • October 2025 announcement positioned this as “India’s entry into advanced node R&D, placing it among the emerging nations advancing research and design at cutting-edge technology nodes”

India semiconductor market projection:

  • 2024-25: ~$45-50bn
  • 2030 projection: $100-110bn
  • Target self-sufficiency: 70-75% of domestic demand by 2029
  • Target advanced node manufacturing: 3nm and 2nm by 2035 (ambitious but stated)

Sources:

Software ecosystem timeline hedge

Claim in prose: “RISC-V has the architectural neutrality the structural argument requires; it does not yet have ARM’s software ecosystem maturity. ARM took roughly a decade after Graviton 1 to reach credible parity with x86 on enterprise software porting; RISC-V is several years behind ARM at the equivalent stage.”

Sources for the timeline calibration:

  • Graviton software ecosystem maturation timeline: AWS public documentation 2018-2024, ARM Neoverse partner reports
  • RISC-V toolchain status: RISC-V International annual reports, GCC/LLVM RISC-V support tracking
  • This is an analytical observation/hedge, not a primary factual claim. Sources cited as calibration evidence.

§7 — What’s left

Counterfactuals

The piece names four scenarios that could materially change the structural argument’s slope:

  1. Intel succeeding as a merchant foundry on advanced nodes
  2. ARM consolidating its licensee base and using Armv9 royalty rates aggressively
  3. A material thaw in the US-China relationship reducing sovereign-compute urgency
  4. The software-ecosystem chasm between RISC-V and production toolchains persisting longer than hardware programmes anticipate

These are scenario hedges, not primary factual claims. No new sources required beyond the §5 (Intel 18A), §6 (ARM Ltd royalty), and §6 (RISC-V software ecosystem) entries above.

TCP/IP analogy in §7

Claim in prose: “TCP/IP outlasted every proprietary networking stack precisely because it was unowned: in a world of competing blocs, the standards that survive are the ones nobody can block.”

This is an analytical analogy, not a primary factual claim. The historical record on proprietary networking stacks (SNA, DECnet, IPX/SPX, AppleTalk, NetBIOS) being supplanted by the unowned TCP/IP standard is reference-level material in network engineering history.

Cross-cutting data — chart sources

Chart I — Volume comparison

CategoryFigureSource
Smartphone SoCs1,200mCounterpoint Research, IDC, 2024 global handset SoC volumes
Apple iPhone alone226mApple SEC filings, IDC
Windows laptop CPUs187mIDC, Mercury Research 2024
Desktop PC CPUs75mIDC, Mercury Research 2024
x86 server CPUs25mMercury Research, combined Intel + AMD server volumes

The Apple iPhone bar (226M) is a subset of the Smartphone SoC bar (1,200M). Chart caveat note explicitly disclaims this to avoid double-counting confusion.

Chart II — Sovereign feasibility matrix

Author analysis. Methodology:

  • “Feasible at scale” (teal, ●): commercial deployment exists at production volumes, with the actor having durable control of the architecture’s critical path
  • “Partial / caveated” (cream, ◐): commercial deployment exists but with structural caveats — for sovereign × ARM, the foreign-licensor dependency demonstrated by the Arm China governance crisis; for hyperscaler × RISC-V, active programmes (Tenstorrent, Alibaba T-Head) and Nvidia’s July 2025 CUDA-on-RISC-V announcement positioning RISC-V as forward-compatible host CPU
  • “Blocked / not feasible” (dark slate, ○): structural constraints prevent the architecture serving the actor’s needs at full scope

Chart III — Binning hierarchy

Wafer → die → bin → product structure derived from:

  • TSMC N3E capacity allocation (~180k wafers/year for iPhone) — see §2 wafer math
  • A18 Pro / A18 die specifications — see §2
  • 2024 average yield ~72%, ramp from ~60% Q4 2023 to low 80s late 2024 — see §2 yield trajectory
  • 14-18% binned tail rate at average yield — see §2 binned tail derivation
  • Resulting 12-15M dies/year of binned A18 Pro — see §2 binned tail derivation
  • A fifth to a third of the global budget laptop CPU market — derived against the 40-60M unit budget laptop market data (see §1 budget laptop market context)